1. Field of the Invention
The present invention generally relates to the design and testing of integrated circuits (ICs), and, more specifically, to a method and circuit for accurately delivering DC or AC voltage to circuit nodes of integrated circuits.
2. Description of Related Art
Automatic Test Equipment (ATE) typically includes a parametric measurement unit (PMU) to measure the drive of an output pin of an IC, or to accurately deliver a DC voltage to an IC pin. The output drive of a pin is tested by applying a known current to the pin and measuring the resultant voltage at the pin, or by applying a known voltage and measuring the resultant current. FIG. 1 shows a simple IC 10, having pins 12 and 14, mounted on a device interface board 16 associated with test equipment 22. A DC stimulus voltage 18 is accurately delivered to pin 12 of the IC by applying (forcing) the stimulus voltage via first conductive path 20 of test equipment 22, and sensing the applied voltage via a second conductive path 24 of the test equipment. Typically, an operational amplifier 26 is used to adjust the applied voltage until the sensed voltage is equal to the desired voltage. A capacitor 64 is typically included to improve the stability of the operational amplifier. The aforementioned conductive paths typically comprise wires, board-to-board interface connectors, and electromechanical relays 28. FIG. 2 illustrates a similar arrangement for testing a circuit 30 having differential pins 32, 34. In this case, the arrangement uses a differential amplifier 36. While these arrangements succeed in accurately delivering a desired voltage to an IC pin, it does not deliver the desired voltage to the circuit node of interest within the circuit. More specifically, the arrangements do not accommodate voltage drops which may occur between the IC pin and the node of interest. It also does not provide a way of applying a high frequency voltage signal.
Saitoh U.S. Pat. No. 6,397,361, granted on May 28, 2002, for “Reduced pin Integrated Circuit I/O Test”, describes force/measure paths of a tester which converge on a single FM (force/measure) pad of an IC under test. The pad is connected to a single, on-chip wire bus that is connected, via transmission gate switches, to other pins of the IC so that they may be tested without mechanically probing them. The tester forces a current and measures a voltage, or, alternatively, forces a voltage and measures a current. If the transmission gates have significant series impedance, for example comparable to the impedance of the pull-up resistance of the pin, then the pin cannot be accurately driven to a stimulus voltage because of the unknown voltage drop across the transmission gate. The patent also shows the addition of a second bus to allow access to differential pin pairs that are inputs to a differential receiver so that two pins can be driven simultaneously. Saitoh is not concerned with and does not provide a method of accurately delivering a voltage to a circuit node within the circuit.